Not interpreted by the SCU as the ACP has no inner cache policy, and are passed to the L2 Cache Controller for use if the cache is setup in exclusive mode. shared attribute must be set to 1 for coherent accesses The AxUser signals are used to pass extra information, and for ACP transactions they are used to pass inner and outer cacheable information. Note: These setting should be altered based on use case Suggested initial value for AW(R)CACHEĪwcache = 0xF // 4'b1111 Write Allocate, Read Allocate, Bufferable, CacheableĪrcache = 0xF // 4'b1111 Write Allocate, Read Allocate, Bufferable, Cacheable Reference: Cortex™-A9 MPCore® Revision: r3p0 Technical Reference Manual (ARM DDI 0407G (ID072711)): 2.4 Accelerator Coherency Port See ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition (ARM DDI 0406C.c (ID051414) ) : A3.5 Memory types and attributes and the memory order model AxCache must be 1 for coherent accesses. The correct AxCache setting is dependent on the MMU Page table settings. The Axi_cache_security bridge can be found in the Arria 10 Bridge example tml The Axi_cache_security bridge should be used to drive AxCache/AxUser/AxProt sideband signals to the correct values. The above is set by default in the latest u-boot-socfpga versions available from ĭriving AXI sideband signals from Qsys: Axi_cache_security bridge Reference: CoreLink™ Level 2 Cache Controller L2C-310, Revision: r3p3 Technical Reference Manual (ARM DDI 0246H (ID080112)): Section 2.3.2 Shareable attribute. The change in the point of coherency could cause problems if masters access the SDRAM via 元 or the FPGA2SDRAM bridge. This setting disables optimizations in the L2 Cache controller which transform some non-cacheable accesses from the MPU cores or ACP port into Cacheable non-allocated accesses, and moves the point of coherency from the SDRAM to the L2 Cache. ![]() It is recommended that the Aux Control register bit : Shared attribute override enable bit is set to ON. Set register fpga2soc_ctrl: allow_secure to 1 (default = 0, don’t allow secure)ĬoreLink™ Level 2 Cache Controller L2C-310 configuration To allow secure access via the FPGA2HPA bridge: The U-boot generated from the SoC EDS software version 16.0 and later disables NOC firewalls, but sets master to disallow secure access. If a master is set to disallow secure accesses, all transaction will be changed to non-secure state, which can break coherency.The master controls must be set to allow/disallow secure accesses.The firewalls must be configured to allow transactions through the bridge.The Arria® 10 SoC Network on Chip iinterconnect(NOC) is configurable with firewalls on each bridge and throughout the interconnect. Note: the NS register will only be available in supervisor mode. Secure mode is enabled if CP15: SDR:NS = 1. Secure should be used for memory to be accessed by a process running in the ARM secure state (not to be confused with supervisor mode).For memory to be accessed from a Linux user space application or Kernel the security mode should be non-secure.The memory must be marked as Write back Write Allocate (WBWA).See Linux and ARM documentation for more detail on MMU page table allocation attributes, and Secure Mode (trust zone). The MMU Page Tables must be set up so as to define the target memory area cacheable, and either secure, or non secure. ![]()
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